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Home Semiconductor Corp. v. Samsung Electronics Co. Ltd.

United States District Court, D. Delaware

August 21, 2019

HOME SEMICONDUCTOR CORPORATION, Plaintiff,
v.
SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS AMERICA INC., SAMSUNG SEMICONDUCTOR INC., and SAMSUNG AUSTIN SEMICONDUCTOR LLC, Defendants.

          MEMORANDUM ORDER

         Presently before the Court is the issue of claim construction of multiple terms in U.S. Patent Nos. 5, 452, 261 ("the '261 patent") and 6, 146, 997 ("the '997 patent"). I have considered the parties' joint claim construction brief. (D.I. 101). I held a Markman hearing on February 14, 2019. (D.I. 152).

         I. BACKGROUND

         The '261 patent relates to a serial address generator for random access memory. '261 patent at 1:6-9. The parties dispute the construction of terms in claims 1, 8-10, and 12-14. The claims provide:

         1. An address generator for a random access memory, comprising:

an address sequencer having a clock input terminal, a preset terminal, and an output terminal;
an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and
an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator;
wherein the address sequencer includes means for incrementally timing the address sequencer to generate a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.

         8. The address generator of claim 1, further comprising means for providing an externally generated address to the address input terminal, wherein the externally generated address is a first address of a page of the random access memory.

         9. An address generator for a random access memory, comprising:

means for providing a first address in a sequence of addresses, the first address being provided from an external source as an output address;
an address sequencer for generating the subsequent addresses in the sequence of addresses, a second address in the sequence being provided as an output address immediately following the generation of the first address;
an internal address enable switch connected between an output terminal of the address sequencer and an output terminal of the address generator;
an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and
means for incrementally timing the address sequencer during a preset period to generate the second address at a same time that the first address is being provided from the external source.

         10. A method of generating a sequence of addresses for addressing a random access memory, comprising the steps of:

providing from an external source a first address in the sequence as an output address;
switching in the first address as an output address during a preset period;
then, providing from an address sequencer a second address in the sequence as an output address, the second address being generated by incremental timing during at least a part of a duration of the step of providing the first address; and
switching in the second address as an output address after the preset period.

         12. An address generator for a random access memory, comprising:

         an address sequencer having a clock input terminal, a preset terminal, and an output terminal;

an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator;
an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and
means for providing a preset signal of a predetermined duration and level to the preset terminal during at least a portion of the duration of the first address, the preset signal setting the address sequencer to the second address in the series;
wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.

         13. An address generator for a random access memory, comprising:

         an address sequencer having a clock input terminal, a preset terminal, and an output terminal;

an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator;
an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and
means for providing clock signals of predetermined level to the clock input terminal, a first of the clock signals occurring only after the duration of the first address;
wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.

         14. An address generator for a random access memory, comprising:

an address sequencer having a clock input terminal, a preset terminal, and an output terminal;
an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and
an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator;
wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch, and
wherein the address sequencer includes a counter having a master portion and a slave portion.

'261 patent at 7:44-8:4, 8:27-66, 9:3-10:30.

         The '997 patent relates to a method of fabricating semiconductor devices, and specifically a method of forming a self-aligned contact hole. '997 patent at 1:6-9. The parties dispute the construction of terms in claims 2 and 9. The relevant claims provide:

         1. A method for forming a self-aligned contact hole, comprising the steps of:

(a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon;
(b) forming a conformal layer of etch barrier material overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode;
(c) forming an insulating layer overlying the barrier layer;
(d) etching an opening through the insulating layer self-aligned and borderless to the diffusion region by using the barrier layer as an etch stop; and
(e) anisotropically etching the barrier layer underneath the opening, thereby exposing the diffusion region and simultaneously forming a spacer of the etch barrier material on the sidewall of the gate electrode.

         2. The method as claimed in claim 1, further comprising a step of forming an oxide layer over the diffusion region and on the sidewalls of the gate electrode by thermal oxidation prior to forming the barrier layer.

         9. A method for forming a self-aligned contact hole, comprising the steps of:

(a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon, said gate electrode comprising a capping layer;
(b) forming an oxide layer over the diffusion region and on the sidewalls of the gate electrode by thermal oxidation;
(c) forming a conformal layer of silicon nitride overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode;
(d) forming an insulating layer overlying the conformal layer of silicon nitride;
(e) etching an opening through the insulating layer self-aligned and borderless to the diffusion region by using the silicon nitride layer as an etch stop; and
(e) anisotropically etching the silicon nitride layer underneath the opening, thereby exposing the diffusion region and simultaneously forming a spacer of silicon nitride on the sidewall of the gate electrode.

'997 patent at 3:54-4:8, 4:26-47.

         II. LEGAL STANDARD

         "It is a bedrock principle of patent law that the claims of a patent define the invention to which the patentee is entitled the right to exclude." Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc) (citation omitted). '"[T]here is no magic formula or catechism for conducting claim construction.' Instead, the court is free to attach the appropriate weight to appropriate sources 'in light of the statutes and policies that inform patent law.'" SoftView LLC v. Apple Inc., 2013 WL 4758195, at *1 (D. Del. Sept. 4, 2013) (quoting Phillips, 415 F.3d at 1324). When construing patent claims, a court considers the literal language of the claim, the patent specification, and the prosecution history. Markman v. Westview Instruments, Inc., 52 F.3d 967, 979-80 (Fed. Cir. 1995) (en banc), aff'd, 517 U.S. 370 (1996). Of these sources, "the specification is always highly relevant to the claim construction analysis. Usually, it is dispositive; it is the single best guide to the meaning of a disputed term." Phillips, 415 F.3d at 1315.

         "[T]he words of a claim are generally given their ordinary and customary meaning. . . . [This is] the meaning that the term would have to a person of ordinary skill in the art in question at the time of the invention, i.e., as of the effective filing date of the patent application." Id. at 1312-13. "[T]he ordinary meaning of a claim term is its meaning to [an] ordinary artisan after reading the entire patent." Id. at 1321. "In some cases, the ordinary meaning of claim language as understood by a person of skill in the art may be readily apparent even to lay judges, and claim construction in such cases involves little more than the application of the widely accepted meaning of commonly understood words." Id. at 1314.

         When a court relies solely upon the intrinsic evidence-the patent claims, the specification, and the prosecution history-the court's construction is a determination of law. See Teva Pharm. USA, Inc. v. Sandoz, Inc., 135 S.Ct. 831, 841 (2015). The court may also make factual findings based upon consideration of extrinsic evidence, which "consists of all evidence external to the patent and prosecution history, including expert and inventor testimony, dictionaries, and learned treatises." Phillips, 415 F.3d at 1317-19. Extrinsic evidence may assist the court in understanding the underlying technology, the meaning of terms to one skilled in the art, and how the invention works. Id. Extrinsic evidence, however, is less reliable and less useful in claim construction than the patent and its prosecution history. Id.

         "A claim construction is persuasive, not because it follows a certain rule, but because it defines terms in the context of the whole patent." Renishaw PLC v. Marposs Societa' per Azioni, 158 F.3d 1243, 1250 (Fed. Cir. 1998). It follows that "a claim interpretation that would exclude the inventor's device is rarely the correct interpretation." Osram GMBH v. Int'l Trade Comm'n, 505 F.3d 1351, 1358 (Fed. Cir. 2007) (citation omitted).

         III. CONSTRUCTION OF AGREED-UPON TERMS

         The Court adopts the following agreed-upon constructions.

         (Image Omitted)[1]

         (Image Omitted.)[2]

         (Image Omitted.) [3]

         IV. CONSTRUCTION OF DISPUTED TERMS

         A. The '261 Patent1. "means for incrementally timing the address sequencer..." (claims 1 and 9); "the second address being generated by incremental timing during at least a part of the duration of the ...


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